1. Technical Field
The present invention relates to a dielectric isolation processing techniques for integrated circuits and, more particularly, to the utilization of a wafer bonding process in the fabrication of dielectrically isolated wafers.
2. Description of the Prior Art
Dielectric isolation (DI) has been used extensively in integrated circuit technology for fabricating high voltage devices which require a relatively large degree of inter-device isolation. In general, the DI process involves etching grooves in a silicon substrate (the grooves delineating the boundaries of the DI regions, often referred to as "tubs"). The etched substrate is then oxidized to form a layer sufficiently thick so as to provide the desired isolation. A relatively thick polysilicon layer, or "handle" is subsequently grown over the oxide. The structure is then inverted and the exposed bottom of the silicon substrate is ground and polished away until the surface of the tub regions is exposed. The polysilicon handle then forms the "substrate" of the final structure. U.S. Pat. No. 4,820,653 issued to W. G. Easter et al. on Apr. 11, 1989 describes in detail the DI process as outlined above. A problem with the conventional DI technique is that the process of growing a thick polysilicon handle is both time-consuming and expensive. Further, the prolonged exposure of the tub regions to the elevated temperature required for polysilicon deposition has been found to degrade the quality of the tub regions themselves. The grown polysilicon handle forms the "substrate" of the final device structure and is inherently of poorer quality (i.e., higher defect density, stress) and a monocrystalline silicon substrate.
An alternative isolation technique, referred to as Silicon On Insulator (SOI) utilizes wafer bonding and a buried oxide layer to provide inter-device isolation. Simply, a first silicon substrate is oxidized over a surface region and a second substrate is bonded to the oxide layer of the first substrate. There exist many different techniques, usually involving heat treatments, to bond the wafers together. An article entitled "Silicon Wafer-Bonding Process Technology for SOI Structures", by T. Abe et al. appearing in Proceedings of 4th Int. Symp. on Silicon-on-Insulator Technology and Devices, May 1990 describes in detail various aspects of the SOI technology. Alone, however, SOI cannot provide inter-device isolation for devices fully contained within the same substrate.
U.S. Pat. No. 4,851,078 issued to J. P. Short et al. on Jul. 28, 1989 utilizes a combination of the above-described processes to form a dielectrically isolated silicon-on-insulator semiconductor device. The Short et al. process, however, requires at least two full wafer bonding sequences of operations (e.g., the bonding together of a series of three wafers) to form the final device structure.
A need remains in the prior art, therefore, for a relatively simple DI process technique which addresses the various limitations described above.